![]() The specific items disclosed in each generation are not the same, and sometimes a generation will have a more verbose explanation that fills in gaps for the other generations. It is helpful to compare and contrast the documentation from all of the recent processor generations. Section 3.1.3 “Reference for M2M Packet Matching”, Table 3-9 “SMI3 Opcodes”, mentions the directory in the description of 10 of the 18 transaction types.These include information on directory states – very helpful for understanding the implementation.M2M Events “DIRECTORY_HIT”, “DIRECTORY_LOOKUP”, “DIRECTORY_MISS”, “DIRECTORY_UPDATE”.Remote socket RFOs will result in a directory update but so will ordinary reads that return data in E state (the default for data reads that hit unshared lines). Aside: it would be easy to be misled by this description.Remote socket RFOs will result in a directory update which, in turn, will cause a write command.” IMC_WRITES_COUNT includes: “NOTE: Directory bits are stored in memory.CHA Events “DIR_LOOKUP” and “DIR_UPDATE”.Specific references in this manual include: The version that I have spent the most time with is for the 1st and 2nd generations of Intel Xeon Scalable Processors (“Skylake Xeon” and “Cascade Lake Xeon”): “Intel® Xeon® Processor Scalable Memory Family Uncore Performance Monitoring Reference Manual”, Intel document 336274. Much of the detailed understanding of the memory directory implementation comes from studying the uncore performance counter events that make reference to memory directories.Īs an example, there are direct references to memory directories in several sections of the Intel Uncore Performance Monitoring Guides for their various processor families. (I apologize in advance if the links are broken - it is hard to keep up with web site reorganizations - but the presentations should be relatively easy to find using web search services.) Implicit Information: ![]() ![]() The Intel Hot Chips presentation on Ivy Bridge EP describes the memory directory feature and says that it was upgraded from one bit to two bits in the IVB-EP processor – describing the 3 states that are still used.The Intel Hot Chips presentation on Westmere-EX describes an early implementation of the memory directory (slides 9-12):.Intel has disclosed various details in some presentation at the Hot Chips series of conferences: The language is not as precise as I would prefer, but there are actually quite a few interesting details in that section. The clearest admission that the memory directory feature exists is in this “technical overview” presentation – in the section “Directory-Based Coherency” –. That was boring, so I am posting my notes here so I can find them again - maybe others will find this useful as well…. When asked for references to public information about the Intel’s memory directory implementation, I had to go back and find the various tiny bits of information scattered around different places. “A Memory Directory is one or more bits per cache line in DRAM that tell the processor whether another socket might have a dirty copy of the cache line.” I have referred to this in various presentations as: This is used in multi-socket systems to reduce cache coherence traffic between sockets. One of the (many) minimally documented features of recent Intel processor implementations is the “memory directory”.
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